1. Field of the Invention
The present invention relates to an ESD protection circuit having a first field-effect transistor, which has a first drain terminal, a first source terminal and a first control terminal (gate), and having an input network which, in the event that a first voltage present between the first drain terminal and the first source terminal crosses a threshold value, alters a second voltage that appears between the first control terminal and the first source terminal.
2. Description of the Background Art
In the handling and use of integrated circuits (IC), it is necessary to protect the components and assemblies contained therein from the effects of overvoltages. In this context, overvoltages are defined as electrical signals such as those arising, for example, from the discharging of static charges, whether from persons or machine parts through an IC or from an IC through persons or machine parts. Such discharge processes are also called electrostatic discharge (ESD). When such discharge processes act on an integrated circuit, irreversible changes in its components or assemblies can occur, for example by burn-through of thin layers (thin-film burn-out), filamentation, and short-circuiting of layer junctions (junction spiking), charge carrier injection in oxide layers or oxide rupture, which under some circumstances leads to destruction of the entire IC. In this context, low voltages are defined as operating voltages for ICs on the order of less than 10 volts.
In conventional ESD protection circuits, the input network consists of two Zener diodes and an ohmic resistance. The two Zener diodes are connected in series with one another, and as a series circuit are connected in parallel with the first voltage, thus in parallel with the channel of the first field-effect transistor. The resistance is located between the first source terminal and a connection of the first control terminal to the center tap of the series circuit.
To dissipate a given ESD current or a given power in the form of a product of ESD current and ESD voltage, the first field-effect transistor must have a comparatively large channel area. In the general trend toward increasing packing densities of integrated circuits, a requirement on the part of the ESD circuit for a large area is fundamentally problematic.